US 12,455,787 B2
Memory system and operating method thereof
Kwang Su Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 28, 2023, as Appl. No. 18/343,113.
Application 18/343,113 is a continuation of application No. 17/191,190, filed on Mar. 3, 2021, granted, now 11,726,878.
Claims priority of application No. 10-2020-0132311 (KR), filed on Oct. 14, 2020.
Prior Publication US 2023/0333932 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/14 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1415 (2013.01) [G06F 3/0602 (2013.01); G06F 3/064 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device including a plurality of super memory blocks; and
a memory controller for communicating with the memory device and controlling the memory device,
wherein the memory controller is configured to:
manage a main read count table including a plurality of first read count table entries, each one of the plurality of first read count table entries corresponding to one of the plurality of super memory blocks, a first read count table entry comprising information on a count of a first read operation executed on a corresponding super memory block, and
manage a partial read count table including a plurality of second read count table entries, a second read count table entry including information on a count of a second read operation executed during a recovery operation for an error, when the error occurs during an operation of reading data stored in one of the plurality of super memory blocks,
wherein the second read count table entry comprises, for a first super memory block corresponding to a read count table entry among the plurality of super memory blocks, a main read count corresponding to the first super memory block and a plurality of sub-read counts corresponding to each of a plurality of sub-areas included in the first super memory block.