US 12,455,767 B2
Data transfer scheduling for hardware accelerator
Monica Man Kay Tang, Santa Clara, CA (US); Ruihua Peng, San Jose, CA (US); and Zhuo Ruan, San Jose, CA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Oct. 19, 2023, as Appl. No. 18/490,572.
Application 18/490,572 is a continuation of application No. 18/173,257, filed on Feb. 23, 2023, granted, now 11,816,502.
Application 18/173,257 is a continuation of application No. 17/191,610, filed on Mar. 3, 2021, granted, now 11,593,164, issued on Feb. 28, 2023.
Prior Publication US 2024/0045719 A1, Feb. 8, 2024
Int. Cl. G06F 9/48 (2006.01); G06F 7/24 (2006.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01)
CPC G06F 9/4881 (2013.01) [G06F 7/24 (2013.01); G06F 9/5027 (2013.01); G06F 9/544 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing device comprising:
a hardware accelerator including a plurality of processing areas and a plurality of memory buffers, wherein:
the plurality of processing areas are arranged in a plurality of processing area groups that each include three or more of the processing areas arranged in a fully connected graph;
each processing area group of the plurality of processing area groups is connected to two or more other processing area groups by a first interconnect ring and a second interconnect ring; and
the hardware accelerator is configured to multi-cast each of a plurality of entries of a first input matrix and a second input matrix to the plurality of processing area groups by transmitting respective identical copies of the entries of the first input matrix and the second input matrix from an initiator processing area or an initiator memory buffer to each of the processing area groups.