| CPC G06F 9/4881 (2013.01) [G06F 9/30036 (2013.01); G06F 9/321 (2013.01); G06F 9/3893 (2013.01); G06F 15/7807 (2013.01); G06N 3/063 (2013.01)] | 20 Claims |

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1. An integrated circuit device comprising:
a counter;
a first hardware block communicably coupled to the counter and configured to operate according to a first schedule that comprises a first set of operations each of which is scheduled to be executed by the first hardware block at a first respective value of the counter; and
a second hardware block communicably coupled to the counter and to the first hardware block, the second hardware block configured to operate according to a second schedule that comprises a second set of operations each of which is scheduled to be executed by the second hardware block at a second respective value of the counter, and
wherein operations of the second schedule are coordinated with operations of the first schedule such that compute operations in the first schedule are executed concurrently with data exchange operations in the second schedule, and that the first schedule triggers the first hardware block to send data to the second hardware block at a first pre-scheduled value of the counter, and the second schedule triggers the second hardware block to accept the data at an input at a second pre-scheduled value of the counter that is after the first pre-scheduled value.
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