US 12,455,745 B2
Processor subroutine cache
Christian Wiencke, Garching (DE)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 7, 2020, as Appl. No. 16/987,895.
Application 16/987,895 is a continuation of application No. 14/245,667, filed on Apr. 4, 2014, granted, now 10,740,105.
Prior Publication US 2020/0364054 A1, Nov. 19, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 12/0875 (2016.01)
CPC G06F 9/3808 (2013.01) [G06F 9/30054 (2013.01); G06F 9/323 (2023.08); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a request for a subroutine;
obtaining a first value associated with the subroutine from a first register, wherein the first value indicates whether or not the subroutine is stored in a first memory that is configured to selectively cache a first set of instruction types including the subroutine instead of a second set of instruction types, and wherein the first value is distinct from an address at which the subroutine is stored in the first memory;
determining, based on the first value, whether the subroutine is stored in the first memory; and
based on the first value indicating that the subroutine is stored in the first memory, retrieving the subroutine from the first memory based on a second value of a second register, wherein the second value indicates the address of the subroutine in the first memory.