US 12,455,740 B2
System and method to control the number of active vector lanes in a processor
Timothy David Anderson, University Park, TX (US); and Duc Quang Bui, Grand Prairie, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 3, 2024, as Appl. No. 18/625,645.
Application 18/625,645 is a continuation of application No. 18/094,611, filed on Jan. 9, 2023, granted, now 11,977,887.
Application 18/094,611 is a continuation of application No. 17/126,156, filed on Dec. 18, 2020, granted, now 11,550,573, issued on Jan. 10, 2023.
Application 17/126,156 is a continuation of application No. 16/236,936, filed on Dec. 31, 2018, granted, now 10,871,965, issued on Dec. 22, 2020.
Application 16/236,936 is a continuation of application No. 14/326,928, filed on Jul. 9, 2014, granted, now 10,175,981, issued on Jan. 8, 2019.
Claims priority of provisional application 61/844,124, filed on Jul. 9, 2013.
Prior Publication US 2024/0248714 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3206 (2019.01); G06F 1/3287 (2019.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30036 (2013.01) [G06F 1/3206 (2013.01); G06F 1/3287 (2013.01); G06F 9/30014 (2013.01); G06F 9/30018 (2013.01); G06F 9/30038 (2023.08); G06F 9/30072 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/3013 (2013.01); G06F 9/3887 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a data path including at least a first lane of a first width and a second lane of a second width that is larger than the first width;
an execution unit configured to execute a first instruction on data of the first width or less using the first lane, and to execute a second instruction on data greater than the first width and less than or equal to the second width using the second lane; and
a control register configured to store a value indicating which of the first and second lanes to be used in instruction execution by the execution unit;
wherein the circuit is configured to, based on the value stored in the control register, power off the first lane when the execution unit executes the second instruction but not the first instruction, and power off the second lane when the execution unit executes the first instruction but not the second instruction.