US 12,455,739 B2
Instruction set architecture for a vector computational unit
Debjit Das Sarma, San Jose, CA (US); Emil Talpes, San Mateo, CA (US); and Peter Joseph Bannon, Woodside, CA (US)
Assigned to Tesla, Inc., Austin, TX (US)
Filed by Tesla, Inc., Austin, TX (US)
Filed on Oct. 19, 2023, as Appl. No. 18/490,672.
Application 18/490,672 is a continuation of application No. 18/156,576, filed on Jan. 19, 2023, granted, now 11,797,304.
Application 18/156,576 is a continuation of application No. 15/920,165, filed on Mar. 13, 2018, granted, now 11,561,791.
Claims priority of provisional application 62/625,249, filed on Feb. 1, 2018.
Prior Publication US 2024/0126547 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 17/16 (2006.01)
CPC G06F 9/30036 (2013.01) [G06F 9/3001 (2013.01); G06F 17/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microprocessor system, comprising:
a vector computational unit that includes a plurality of processing elements, wherein each processing element is connected to a corresponding computation unit in a last row of a plurality of computation units included in a computational array and each processing element is connected to a memory,
wherein information associated with a row of data elements is provided in parallel to the plurality of processing elements by the computational array and the memory; and
a control unit circuit configured to provide at least a processor instruction to the vector computational unit, the control unit circuit being configured to synchronize receipt of the information from the computational array and the memory to respective processing elements,
wherein each of the plurality of processing elements of the vector computational unit is configured to process the information in response to the processor instruction,
wherein the processor instruction specifies at least a register in the memory, and wherein one or more processing elements of the plurality of processing elements load the information from the register.