US 12,455,738 B2
Large-scale matrix restructuring and matrix-scalar operations
Robert Pawlowski, Beaverton, OR (US); Ankit More, San Mateo, CA (US); Vincent Cave, Hillsboro, OR (US); Sriram Aananthakrishnan, Portland, OR (US); Jason M. Howard, Portland, OR (US); and Joshua B. Fryman, Corvallis, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 25, 2020, as Appl. No. 17/134,251.
Claims priority of provisional application 63/083,912, filed on Sep. 26, 2020.
Prior Publication US 2022/0100508 A1, Mar. 31, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 17/16 (2006.01); G06F 7/544 (2006.01); G06N 3/08 (2023.01)
CPC G06F 9/30032 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/3818 (2013.01); G06F 7/5443 (2013.01); G06F 17/16 (2013.01); G06N 3/08 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a hardware instruction decoder to decode a single instruction having a first operand to reference a base address of a first representation of a source matrix, a second operand to reference a base address of second representation of a destination matrix, and a third operand to specify one of a plurality of fill values, wherein the plurality of fill values includes a zero and a one; and
execution circuitry to perform one or more operations corresponding to the single instruction, including:
copying elements of the source matrix to same element locations in the destination matrix; and
filling empty element locations of the destination matrix with the one of the plurality of fill values.