US 12,455,723 B2
MAC processing pipeline having activation circuitry, and methods of operating same
Frederick A. Ware, Los Altos Hills, CA (US); and Cheng C. Wang, San Jose, CA (US)
Assigned to Analog Devices, Inc., Wilmington, MA (US)
Filed by Analog Devices, Inc., Wilmington, MA (US)
Filed on Jan. 18, 2022, as Appl. No. 17/577,454.
Claims priority of provisional application 63/144,553, filed on Feb. 2, 2021.
Prior Publication US 2022/0244917 A1, Aug. 4, 2022
Int. Cl. G06F 7/544 (2006.01)
CPC G06F 7/5443 (2013.01) 22 Claims
OG exemplary drawing
 
19. An integrated circuit comprising:
a plurality MAC pipelines including:
a first MAC pipeline including a plurality of multiplier-accumulator circuits connected in series to form a first linear pipeline to process first data input to the first MAC pipeline, via performing a plurality of concatenated multiply and accumulate operations, and to generate first MAC output data based thereon, wherein:
each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits of the first MAC pipeline includes:
a multiplier to multiply first data by a multiplier weight data and generate a first product data, and
an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to generate first sum data using the first product data of the associated multiplier; and
a second MAC pipeline including a plurality of multiplier-accumulator circuits connected in series to form a second linear pipeline to process second data input to the second MAC pipeline, via performing a plurality of concatenated multiply and accumulate operations, and to generate second MAC output data based thereon, wherein:
each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits of the second MAC pipeline includes:
a multiplier to multiply second data by a multiplier weight data and generate a second product data, and
an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to generate second sum data using the second product data of the associated multiplier; and
a first activation circuit, connected to the output of the first MAC pipeline, wherein the first activation circuit is dedicated to and associated with first MAC pipeline and is connected to the output of the first MAC pipeline to receive and process the first MAC output data therefrom, via a first activation function, to generate first MAC pipeline output data using the first MAC output data from the first MAC pipeline;
a second activation circuit, connected to the output of the second MAC pipeline, wherein the second activation circuit is dedicated to and associated with second MAC pipeline and is connected to the output of the second MAC pipeline to receive and process the second MAC output data therefrom, via a second activation function, to generate second MAC pipeline output data using the second MAC output data from the second MAC pipeline; and
wherein:
the first and second MAC pipelines concurrently process the first and second data, respectively; and
the first and second activation circuits concurrently process the first and second MAC output data, respectively.