	US 12,455,722 B2
	Floating-point decomposition circuitry with dynamic precision
Roberto DiCecco, Toronto (CA); Joshua Fender, East York (CA); and Shane O'Connell, Toronto (CA)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 28, 2023, as Appl. No. 18/399,381.
Application 18/399,381 is a continuation of application No. 16/818,889, filed on Mar. 13, 2020.
Prior Publication US 2024/0126506 A1, Apr. 18, 2024
Int. Cl. G06F 7/485 (2006.01); G06F 7/483 (2006.01); G06F 7/487 (2006.01); G06F 7/499 (2006.01); G06F 7/544 (2006.01); G06F 17/16 (2006.01)

CPC G06F 7/485 (2013.01) [G06F 7/483 (2013.01); G06F 7/4876 (2013.01); G06F 7/49947 (2013.01); G06F 7/5443 (2013.01); G06F 17/16 (2013.01)]

20 Claims

1. An integrated circuit, comprising:

first circuitry configurable to:

receive a first floating point number and a second floating point number; and

dynamically choose a precision to convert the first floating point number and the second floating point number into a plurality of components, wherein the plurality of components has a precision less than a precision of at least one of the first floating point number or of the second floating point number; and

second circuitry configurable to perform multiplication operations using the plurality of components.