US 12,455,701 B2
Scalable access control checking for cross-address-space data movement
Narayan Ranganathan, Bangalore (IN); Philip R. Lantz, Cornelius, OR (US); Rajesh M. Sankaran, Portland, OR (US); Sanjay Kumar, Hillsboro, OR (US); Saurabh Gayen, Portland, OR (US); Nikhil Rao, Bengaluru (IN); Utkarsh Y. Kakaiya, Folsom, CA (US); Dhananjay A. Joshi, Portland, OR (US); David Jiang, Chandler, AZ (US); and Ashok Raj, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 1, 2022, as Appl. No. 17/711,928.
Claims priority of provisional application 63/226,159, filed on Jul. 27, 2021.
Prior Publication US 2023/0032586 A1, Feb. 2, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 9/455 (2018.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45583 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory to store an Inter-Domain Permissions Table (IDPT) having a plurality of entries, wherein a single entry of the IDPT is to provide a relationship between an access address space identifier and a plurality of submitter address space identifiers; and
a hardware accelerator device to allow access to an access address space, corresponding to the access address space identifier, by one or more submitters, corresponding to the plurality of submitter address space identifiers, respectively, based at least in part on the relationship provided by the single entry of the IDPT, wherein allowing the access comprises finding the single entry within the IDPT, the single entry being capable of identifying the plurality of submitter address space identifiers including submitter address space identifiers that correspond to the one or more submitters.