US 12,455,700 B2
Increased shift frequency for multi-chip-module scan
Nehal Patel, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Mar. 31, 2023, as Appl. No. 18/194,390.
Prior Publication US 2025/0208779 A1, Jun. 26, 2025
Int. Cl. G06F 3/06 (2006.01); G06F 1/06 (2006.01)
CPC G06F 3/0647 (2013.01) [G06F 1/06 (2013.01); G06F 3/0604 (2013.01); G06F 3/0683 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
an input and an output;
a plurality of data storage elements serially connected between the input and the output and comprising a portion of a chain of data storage elements;
a bypass circuit coupled to the input and the output; and
a control circuit configured to:
enable, in response to a first trigger that corresponds to the portion of the chain of data storage elements initiating a data dump, the plurality of data storage elements to shift data through the plurality of data storage elements to the output;
enable, in response to a second trigger that corresponds to the portion of the chain of data storage elements having completed the data dump, the bypass circuit to shift data from the input to the output; and
disable, in response to the second trigger, the plurality of data storage elements.