US 12,455,694 B2
Input-output memory management unit with memory protection
Yu-Tien Chang, Hsinchu (TW); Lin-Ming Hsu, Hsinchu (TW); and Chun-Ming Chou, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Dec. 14, 2023, as Appl. No. 18/540,739.
Claims priority of provisional application 63/387,285, filed on Dec. 14, 2022.
Prior Publication US 2024/0201874 A1, Jun. 20, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0622 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0673 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system on chip, comprising:
a dynamic random access memory (DRAM) controller, comprising:
a secure range (SR) table configured to store a start address, an end address, and enabled registers of each secure range; and
an access identification (AID) permission table configured to store access permissions of secure ranges of each access identification;
a secure range permission checker embedded in the dynamic random access memory (DRAM) controller or a bus and linked to the secure range (SR) table and the access identification (AID) permission table, and configured to check the access permissions of the secure ranges according to the access identification (AID) permission table; and
a plurality of intellectual property (IP) cores linked to the dynamic random access memory (DRAM) controller, and comprising a translation lookaside buffer (TLB) comprising an input-output memory management unit (IOMMU) table or an input-output memory protection unit (IOMPU) table to store secure range information, each IP core being configured to access specific data in a DRAM according to the secure range information;
wherein when a virtual address pointed by the input-output memory management unit (IOMMU) table has a same physical address pointed by the input-output memory protection unit (IOMPU) table, the virtual address and the physical address direct to identical secure range information.