US 12,455,690 B2
Page buffer, semiconductor memory having the same, and operating method thereof
Han Seo, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 8, 2022, as Appl. No. 18/077,915.
Claims priority of application No. 10-2022-0093599 (KR), filed on Jul. 28, 2022.
Prior Publication US 2024/0036742 A1, Feb. 1, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A page buffer comprising:
a first current supply circuit connected to a bit line, the first current supply circuit configured to connect or block a power voltage node to or from a common sensing node based on a potential level of the bit line;
a second current supply circuit configured to control a potential level of a sensing node based on a current amount of the common sensing node; and
a latch unit configured to latch data based on a potential of the sensing node.