US 12,455,614 B2
Power limiting in a processor-based system based on allocating power budgets for different sub-systems based on multiple time-based power limits
Mahadevamurty Nemani, San Diego, CA (US); Matthew Severson, Austin, TX (US); Gabriel Watkins, San Diego, CA (US); Vijayakumar Ashok Dibbad, Bangalore (IN); Ronald Alton, Oceanside, CA (US); Lai Xu, San Diego, CA (US); and Jeffrey Gemar, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 27, 2023, as Appl. No. 18/475,371.
Prior Publication US 2025/0103130 A1, Mar. 27, 2025
Int. Cl. G06F 1/26 (2006.01); G06F 1/32 (2019.01); G06F 1/3206 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/3296 (2013.01) [G06F 1/3206 (2013.01)] 35 Claims
OG exemplary drawing
 
1. A power limiter circuit for limiting power consumption in a processor-based system comprising a processing unit (PU) sub-system comprising one or more PUs, the power limiter circuit configured to:
(a) compare a PU sub-system current power consumption indicating a first current power consumption in the PU sub-system to each of one or more PU sub-system time-based power limits;
(b) compare a system current power consumption indicating a second current power consumption in the processor-based system to each of one or more system time-based power limits;
(c) generate one or more first PU sub-system power limit budgets based on the comparison of the PU sub-system current power consumption in the PU sub-system, to the one or more PU sub-system time-based power limits;
(d) generate one or more second PU sub-system power limit budgets based on the comparison of the system current power consumption in the processor-based system, to respective one or more system time-based power limits;
(e) generate a total PU sub-system power limit budget based on a lower power limit budget among the one or more first PU sub-system power limit budgets and the one or more second PU sub-system power limit budgets; and
(f) cause a power consumption in the PU sub-system to be constrained to the total PU sub-system power limit budget.