US 12,455,612 B2
Device, method and system to provide thread scheduling hints to a software process
Vadim Bassin, Raanana (IL); Eliezer Weissmann, Haifa (IL); Efraim Rotem, Haifa (IL); and Julius Mandelblat, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 13, 2021, as Appl. No. 17/374,728.
Prior Publication US 2023/0018828 A1, Jan. 19, 2023
Int. Cl. G06F 1/3293 (2019.01); G06F 1/3228 (2019.01); G06F 9/48 (2006.01)
CPC G06F 1/3293 (2013.01) [G06F 1/3228 (2013.01); G06F 9/4887 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
multiple cores comprising:
one or more first cores each of a first type which corresponds to a first level of power consumption; and
a plurality of second cores each of a second type which corresponds to a second level of power consumption which is less than the first level of power consumption; and
power control unit circuitry coupled to the multiple cores, the power control unit circuitry to:
detect an inefficiency of a first operational mode of the processor, wherein the power control unit circuitry is to detect that during the inefficiency, an indication of an amount of power, to be available to the processor, would be below a threshold level;
perform an access of reference information based on the inefficiency, wherein the reference information is to indicate:
a first prioritization of the first type over the second type with respect to removal from a pool of cores which are to be available each as a respective candidate to be selected by a thread scheduler process which is to be executed with the processor; and
a second prioritization of the second type over the first type with respect to addition to the pool of cores;
based on the access of the reference information, perform an identification of:
a first one or more cores of the multiple cores according to the first prioritization; or
a second one or more cores of the multiple cores according to the second prioritization; and
based on the identification, communicate, to an operating system (OS) which is to be executed with the processor, a hint that the processor is to transition to a second operational mode, wherein:
the hint is to indicate to the OS that the processor is to deactivate the first one or more cores, comprising the hint is to indicate to the OS that the first one or more cores are to be removed from the pool of cores; or
the hint is to indicate to the OS that the processor is to activate the second one or more cores, comprising the hint is to indicate to the OS that the second one or more cores are to be added to the pool of cores.