US 12,455,611 B2
Power optimization for camera devices
Alok Kediya, Hyderabad (IN); Manish Poddar, Burhanpur (IN); Suresh Vankadara, Hyderabad (IN); Mukund Mittal, Hyderabad (IN); and Gaurav Gagrani, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jul. 7, 2023, as Appl. No. 18/349,082.
Prior Publication US 2025/0013285 A1, Jan. 9, 2025
Int. Cl. G06F 1/3287 (2019.01); G06F 1/08 (2006.01); G06F 1/3234 (2019.01); G06F 1/3237 (2019.01); G06F 1/324 (2019.01)
CPC G06F 1/3287 (2013.01) [G06F 1/3237 (2013.01); G06F 1/324 (2013.01); G06F 1/08 (2013.01); G06F 1/3234 (2013.01)] 28 Claims
OG exemplary drawing
 
1. An apparatus for data processing, comprising:
at least one memory; and
at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor is configured to:
obtain an indication of a set of sensors that are connected to at least one clock source at a device;
detect whether each of the set of sensors is active or inactive;
select a clock configuration for a set of hardware components at the device based on the detection of whether each of the set of sensors is active or inactive, wherein the clock configuration is associated with the at least one clock source;
set a clock control for each of the set of hardware components based on the selected clock configuration, wherein the clock control is associated with the at least one clock source, wherein the setting of the clock control for each of the set of hardware components corresponds to an enablement of a number of bits for an amount of active sensors in the set of sensors; and
output an indication of the selected clock configuration for the set of hardware components at the device.