| CPC G06F 1/3287 (2013.01) | 18 Claims |
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1. A computation processing device, comprising:
a memory unit that retains computation data for weighting computation, and at least a part of which is a non-volatile storage region;
a computation circuit unit that performs computation processing including the weighting computation by using a part or all of the computation data input from the memory unit;
a power gate unit that blocks power supply to a part or all of memory cells other than memory cells storing a part or all of the computation data input to the computation circuit unit in the computation processing when performing the computation processing, in the non-volatile storage region;
a data length setting unit that sets an effective data length with respect to the computation data set in advance, for each computation processing piece of the computation circuit unit,
wherein the computation circuit unit performs the computation processing to a portion of the computation data of the set effective data length,
the power gate unit blocks power supply to memory cells storing a data portion other than the effective data length of the computation data among each of the memory cells in the non-volatile storage region, as memory cells other than memory cells storing a part of the computation data,
the memory unit retains weight data to be a weight of the weighting computation and element data to be weighted, as the computation data,
the computation circuit unit includes a sum-of-product computation circuit including a multiplier performing multiplication of the weight data and the element data, a register, and an adder retaining an addition result obtained by adding a multiplication result by the multiplier and data retained in the register, and
the power gate unit blocks power supply to unused bit cells in the register, on the basis of the effective data length.
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