US 12,455,590 B2
Clock manager redundancy for time synchronized networks
Vuk Lesi, Cornelius, OR (US); Christopher Gutierrez, Hillsboro, OR (US); Shabbir Ahmed, Beaverton, OR (US); Marcio Juliato, Portland, OR (US); and Manoj Sastry, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 26, 2022, as Appl. No. 17/974,113.
Prior Publication US 2024/0143020 A1, May 2, 2024
Int. Cl. G06F 1/12 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/10 (2013.01); G06F 1/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a clock circuitry to manage a clock for a device;
a first processing circuitry coupled to the clock circuitry, the first processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network;
a hardened execution environment coupled to the clock circuitry and the first processing circuitry, the hardened execution environment to comprise:
a detector to monitor the clock manager and generate an alert when the detector identifies abnormal behavior of the clock manager based on predictions of the clock manager control information; and
a second processing circuitry to execute instructions to perform operations for a redundant clock manager, the redundant clock manager to generate model control information based on a clock manager model comprising an analytical model representing a behavior of the clock manager, the redundant clock manager to take over the operations for the clock manager in response to the alert from the detector; and
wherein the first processing circuitry and the second processing circuitry are co-located on the device.