US 12,455,480 B2
Display substrate and display apparatus
Junming Chen, Beijing (CN); Ying Chen, Beijing (CN); Xiaoyuan Wang, Beijing (CN); Xun Pu, Beijing (CN); Bin Wan, Beijing (CN); Guodong Yang, Beijing (CN); Jiandong Guo, Beijing (CN); Zhongshan Wu, Beijing (CN); Yan Liu, Beijing (CN); Yuanyuan Zhu, Beijing (CN); and Dong Wang, Beijing (CN)
Assigned to CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Chongqing (CN); and Beijing BOE Technology Development Co., Ltd, Beijing (CN)
Appl. No. 18/292,101
Filed by Chongqing BOE Optoelectronics Technology Co., Ltd., Chongqing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 30, 2022, PCT No. PCT/CN2022/123386
§ 371(c)(1), (2) Date Jan. 25, 2024,
PCT Pub. No. WO2024/065728, PCT Pub. Date Apr. 4, 2024.
Prior Publication US 2025/0093718 A1, Mar. 20, 2025
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1368 (2006.01)
CPC G02F 1/136286 (2013.01) [G02F 1/1368 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a substrate comprising a first region and a second region at a periphery of the first region; and
a plurality of gate lines and a plurality of data lines on the substrate, wherein the plurality of gate lines and the plurality of data lines are intersected with each other to define a plurality of pixel regions in the first region; wherein the plurality of pixel regions comprise a plurality of normal pixel regions and a plurality of redundant pixel regions at a periphery of the normal pixel regions;
wherein each normal pixel region is provided with a first pixel electrode and a first transistor, each redundant pixel region is provided with a second pixel electrode and a second transistor, a gate of the first transistor is connected to a corresponding gate line, a source of the first transistor is connected to a corresponding data line, and a drain of the first transistor is connected to the first pixel electrode; and
the second pixel electrode and the second transistor are insulated and spaced apart from each other,
wherein the display substrate further comprises:
a first insulation layer on a side of the first transistor away from the substrate; and
a second insulation layer on a side of the first insulation layer away from the substrate;
wherein the first pixel electrode is connected to the drain of the first transistor through a first via running through the first insulation layer and the second insulation layer,
wherein the plurality of redundant pixel regions comprise a first redundant pixel region in which a connection part is disposed, and the connection part is in the same layer as, and insulated and spaced apart from, a source and a drain of the second transistor; and
in the first redundant pixel region, the second pixel electrode is on a side of the second insulation layer away from the substrate, and electrically connected to the connection part through a second via running through the first insulation layer and the second insulation layer.