US 12,455,420 B2
Photonic semiconductor device and method of manufacture
Chen-Hua Yu, Hsinchu (TW); and Hsing-Kuo Hsia, Jhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 10, 2022, as Appl. No. 17/818,809.
Application 17/818,809 is a division of application No. 16/929,799, filed on Jul. 15, 2020, granted, now 12,092,861.
Claims priority of provisional application 62/906,978, filed on Sep. 27, 2019.
Prior Publication US 2022/0382003 A1, Dec. 1, 2022
Int. Cl. G02B 6/42 (2006.01); G02B 6/12 (2006.01); G02B 6/124 (2006.01); G02B 6/13 (2006.01); G02B 6/136 (2006.01); G02B 6/30 (2006.01); G02B 6/34 (2006.01); H04Q 11/00 (2006.01)
CPC G02B 6/4214 (2013.01) [G02B 6/12002 (2013.01); G02B 6/12004 (2013.01); G02B 6/13 (2013.01); G02B 6/136 (2013.01); G02B 6/30 (2013.01); G02B 6/4206 (2013.01); G02B 6/4245 (2013.01); G02B 6/4274 (2013.01); H04Q 11/0005 (2013.01); G02B 2006/12061 (2013.01); G02B 2006/12107 (2013.01); G02B 2006/12121 (2013.01); G02B 2006/12123 (2013.01); G02B 2006/12147 (2013.01); G02B 6/124 (2013.01); G02B 6/34 (2013.01); G02B 6/4204 (2013.01); G02B 6/428 (2013.01); H04Q 2011/0035 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
patterning a silicon layer to form a waveguide;
forming a plurality of photonic components in the waveguide;
forming a grating coupler in the waveguide;
forming an interconnect structure over the waveguide and the plurality of photonic components, wherein the interconnect structure is electrically connected to the plurality of photonic components;
forming a plurality of computing sites on the interconnect structure, wherein forming each computing site of the plurality of computing sites comprises directly bonding a first semiconductor device to the interconnect structure, wherein the first semiconductor device of each computing site is electrically connected through the interconnect structure to at least one photonic component of the plurality of photonic components;
forming a dielectric layer on the interconnect structure and surrounding the first semiconductor devices of the plurality of computing sites; and
performing a planarization process on the dielectric layer, wherein top surfaces of the dielectric layer and top surfaces of the first semiconductor devices are level after performing the planarization process.