US 12,455,391 B2
Reset-type charge-sensitive amplifying circuit, and method for amplifying and resetting data signal
Weizong Xu, Nanjing (CN); Hao Qu, Nanjing (CN); Hai Lu, Nanjing (CN); Jiuzhou Zhao, Nanjing (CN); Dong Zhou, Nanjing (CN); Fangfang Ren, Nanjing (CN); and Feng Zhou, Nanjing (CN)
Assigned to NANJING UNIVERSITY, Nanjing (CN); and Hefei National Laboratory, Hefei (CN)
Filed by NANJING UNIVERSITY, Nanjing (CN); and Hefei National Laboratory, Hefei (CN)
Filed on Apr. 8, 2025, as Appl. No. 19/173,746.
Claims priority of application No. 202411421681.9 (CN), filed on Oct. 12, 2024.
Prior Publication US 2025/0237772 A1, Jul. 24, 2025
Int. Cl. G01T 1/24 (2006.01)
CPC G01T 1/247 (2013.01) 15 Claims
OG exemplary drawing
 
1. A reset-type charge-sensitive amplifying circuit, comprising a signal input buffer module, a signal output amplifying module, and a reset pulse signal generation module, wherein
the signal input buffer module is electrically connected to the signal output amplifying module, and comprises a signal input buffer unit and a voltage bias unit; the signal input buffer unit is provided with a first terminal electrically connected to a semiconductor radiation detector and a second terminal electrically connected to the voltage bias unit, and configured for reading a first output signal output by the semiconductor radiation detector, amplifying the first output signal, and outputting a first amplified signal to the signal output amplifying module, wherein the first amplified signal represents a signal obtained by amplifying the first output signal;
the signal output amplifying module is electrically connected to the reset pulse signal generation module, and configured to perform amplification and high-pass filtering processing on the first amplified signal to obtain and output a target signal;
the reset pulse signal generation module comprises a voltage comparison unit, a reset pulse width modulation unit, and a reset pulse amplifying unit; a first terminal of the voltage comparison unit is electrically connected to the signal output amplifying module, a second terminal of the voltage comparison unit is electrically connected to a first terminal of the reset pulse width modulation unit, and a second terminal of the reset pulse width module unit is electrically connected to the reset pulse amplifying unit, for, based on the first amplified signal, outputting a high-level first control signal by the voltage comparison unit to the reset pulse width modulation unit, and, based on the high-level first control signal, outputting a reset pulse signal by the reset pulse width modulation unit to the reset pulse amplifying unit to reset the reset-type charge-sensitive amplifying circuit;
wherein the signal input buffer unit comprises a silicon carbide-based junction field-effect transistor and a diode, wherein
the signal input buffer unit being provided with the first terminal electrically connected to the semiconductor radiation detector and the second terminal electrically connected to the voltage bias unit, comprises:
the silicon carbide-based junction field-effect transistor being provided with a gate electrically connected to a first terminal of the diode and the semiconductor radiation detector, a drain electrically connected to the voltage bias unit, and a source grounded, for amplifying the first output signal to obtain the first amplified signal, and transmitting the first amplified signal to the signal output amplifying module;
the diode being provided with the first terminal electrically connected to the gate of the silicon carbide-based junction field-effect transistor and the semiconductor radiation detector, and a second terminal electrically connected to a second terminal of the reset pulse amplifying unit, for enabling the first terminal of the diode to be a high-level first output signal when the reset pulse signal of the second terminal of the diode is a high-pulse signal.