US 12,455,317 B2
Logic BIST circuit and semiconductor device including same
Sangsoon Im, Suwon-si (KR); and Sungcheol Park, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 9, 2024, as Appl. No. 18/659,942.
Claims priority of application No. 10-2023-0080679 (KR), filed on Jun. 22, 2023; and application No. 10-2023-0121271 (KR), filed on Sep. 12, 2023.
Prior Publication US 2024/0426909 A1, Dec. 26, 2024
Int. Cl. G01R 31/3185 (2006.01); G01R 31/3181 (2006.01)
CPC G01R 31/318555 (2013.01) [G01R 31/3181 (2013.01); G01R 31/318536 (2013.01); G01R 31/318541 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A logic built-in self-test (BIST) circuit comprising:
a first OR gate configured to receive a scan enable signal and a first register setting signal, and generate a first modified scan enable signal;
a first clock gating circuit configured to receive a first clock and output a first enable clock, according to the first modified scan enable signal and a first function enable signal;
a first scan chain configured to load first scan data into first flip-flops according to the first enable clock, capture an output of a first logic circuit connected to the first flip-flops, and output captured data;
a second OR gate configured to receive the scan enable signal and a second register setting signal, and generate a second modified scan enable signal;
a second clock gating circuit configured to receive a second clock and output a second enable clock, according the second modified scan enable signal and a second function enable signal; and
a second scan chain configured to load second scan data into second flip-flops according to the second enable clock, capture an output of a second logic circuit connected to the second flip-flops, and output the captured data,
wherein at least one of the first clock gating circuit and the second clock gating circuit is configured to output a corresponding enable clock, irrespective of a corresponding function enable signal, when a corresponding register setting signal has a first logic value.