US 12,455,316 B2
Checking data integrity by comparing error-check signals generated on different clock cycles
Ross Martin Torkington, Hertfordshire (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Feb. 27, 2024, as Appl. No. 18/588,819.
Claims priority of application No. 2302801 (GB), filed on Feb. 27, 2023.
Prior Publication US 2024/0319272 A1, Sep. 26, 2024
Int. Cl. G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G06F 11/10 (2006.01)
CPC G01R 31/318525 (2013.01) [G01R 31/31725 (2013.01); G06F 11/1048 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A circuit comprising:
a set of one or more payload flip-flops, arranged to receive an input instance of a payload signal comprising a respective binary signal being input to each of the payload bit flip-flops, and to output an output instance of the payload signal comprising a respective binary value as currently latched into each payload-bit flip-flop;
error check signal generating circuitry arranged to perform an operation on the output instance of the payload signal to generate a first instance of an error check signal comprising one or more bits;
a respective one or more error check flip-flops arranged to receive the one or more bits of the first instance of the error check signal from the error check signal generating circuitry, and to output a second instance of the error check signal comprising a respective binary value as currently latched into each error check flip-flop;
a clock arranged to generate a clock signal which clocks the input instance of the payload signal into the set of payload flip-flops if a payload enable signal of the payload flip-flops is currently asserted, and which clocks the first instance of the error-check signal into the one or more error check flip-flops if an error check enable signal of the error check flip-flops is currently asserted; and
timing control circuitry and comparison circuitry, wherein:
the timing control circuitry is configured to input the input instance of the payload signal to the set of payload flip-flops over two cycles of the clock signal, a first cycle and a second cycle following the first cycle, and to hold the payload enable signal as asserted for the two clock cycles so as to latch the input instance of the payload signal into the payload flip-flops in each of the first and second cycles;
the timing control circuitry is further configured to assert the error check enable signal on the second of the two cycles, so as to latch the first instance of the error check signal into the at least one error check flip-flop on the second cycle; and
the comparison circuitry is arranged so as, at least on the second cycle, to compare the first instance of the error check signal from the error check signal generating circuitry with the second instance of the error check signal from the one or more error check flip-flops and assert an error signal if the first and second instances do not match.