US 12,455,315 B2
Chip with power-glitch detection and power-glitch self-testing
Pin-Wen Chen, Hsinchu (TW); and Kuan-Chung Chen, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsinchu (TW)
Filed on Nov. 21, 2022, as Appl. No. 18/057,315.
Claims priority of provisional application 63/376,628, filed on Sep. 22, 2022.
Claims priority of provisional application 63/296,503, filed on Jan. 5, 2022.
Prior Publication US 2023/0213579 A1, Jul. 6, 2023
Int. Cl. G01R 31/317 (2006.01)
CPC G01R 31/31721 (2013.01) [G01R 31/31704 (2013.01); G01R 31/31706 (2013.01); G01R 31/31713 (2013.01); G01R 31/31719 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip with power-glitch detection and power-glitch self-testing, comprising:
a processor, having a power terminal configured to receive power;
a glitch detector, coupled to the power terminal of the processor for power-glitch detection;
a self-testing circuit, including a glitch generator and a glitch controller controlling the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector, wherein the glitch controller includes a phase-locked loop that generates a clock signal, shift registers operating according to the clock signal generated by the phase-locked loop, and a pulse generator driven by the shift registers to generate a pulse signal that is sent to the glitch generator to determine a pulse width of the self-testing glitch signal; and
a frequency meter, configured to monitor malfunctions of the phase-locked loop or the shift registers.