US 12,454,770 B2
Epitaxial silicon wafer and method for producing the same
Masayuki Miura, Tokyo (JP)
Assigned to SUMCO CORPORATION, Tokyo (JP)
Filed by SUMCO CORPORATION, Tokyo (JP)
Filed on Dec. 3, 2024, as Appl. No. 18/966,952.
Claims priority of application No. 2023-204700 (JP), filed on Dec. 4, 2023; and application No. 2024-205250 (JP), filed on Nov. 26, 2024.
Prior Publication US 2025/0179686 A1, Jun. 5, 2025
Int. Cl. B32B 3/10 (2006.01); B32B 3/20 (2006.01); C30B 15/20 (2006.01); C30B 25/20 (2006.01); C30B 29/06 (2006.01); C30B 30/04 (2006.01); H10D 62/60 (2025.01)
CPC C30B 25/20 (2013.01) [B32B 3/10 (2013.01); B32B 3/20 (2013.01); C30B 15/203 (2013.01); C30B 29/06 (2013.01); C30B 30/04 (2013.01); H10D 62/60 (2025.01)] 27 Claims
OG exemplary drawing
 
1. An epitaxial wafer comprising a silicon substrate and an epitaxial layer on top of the silicon substrate, the epitaxial wafer further including crystal-originated particles (COPs) throughout the silicon substrate, wherein an average size of COPs in a region within 5 mm radially of a wafer edge is 75 nm or less.