US 12,127,487 B2
Low current RRAM-based crossbar array circuits implemented with interface engineering technologies
Minxian Zhang, Amherst, MA (US); and Ning Ge, Danville, CA (US)
Assigned to TetraMem Inc., Fremont, CA (US)
Filed by TetraMem Inc., Fremont, CA (US)
Filed on Nov. 23, 2022, as Appl. No. 18/058,337.
Application 18/058,337 is a division of application No. 16/921,926, filed on Jul. 6, 2020, granted, now 11,527,712.
Prior Publication US 2023/0087409 A1, Mar. 23, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01)
CPC H10N 70/826 (2023.02) [H10B 63/80 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02)] 5 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a substrate;
a bottom electrode formed on the substrate;
a first base oxide layer formed on the bottom electrode;
a first geometric confining layer formed on the first base oxide layer, wherein the first geometric confining layer comprises a first plurality of pin-holes;
a second base oxide layer formed on the first geometric confining layer and connected to a first top surface of the first base oxide layer via the first plurality of pin-holes; and
a top electrode formed on the second base oxide layer,
wherein the first base oxide layer comprises TaOx, HfOx, TiOx, ZrOx, or a combination thereof, wherein the first geometric confining layer comprises Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or a combination thereof, and wherein a conductive filament forms within the first base oxide layer and the second base oxide layer in alignment with the first plurality of pin-holes when a set signal is applied to the top electrode and the bottom electrode.