CPC H10B 61/00 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] | 9 Claims |
1. A method for fabricating a semiconductor device, comprising:
forming a magnetic tunneling junction (MTJ) on a substrate;
forming a top electrode on the MTJ;
forming a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ;
forming a landing layer on the first IMD layer and a sidewall of the first IMD layer; and
patterning the landing layer to form a landing pad on the top electrode and the first IMD layer.
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