US 12,127,399 B2
Array boundary structure to reduce dishing
Meng-Han Lin, Hsinchu (TW); Te-Hsin Chiu, Miaoli County (TW); Wei-Cheng Wu, Zhubei (TW); Li-Feng Teng, Hsinchu (TW); and Chien-Hung Chang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 25, 2023, as Appl. No. 18/323,458.
Application 17/555,828 is a division of application No. 16/022,702, filed on Jun. 29, 2018, granted, now 11,211,388, issued on Dec. 28, 2021.
Application 18/323,458 is a continuation of application No. 17/555,828, filed on Dec. 20, 2021, granted, now 11,706,914.
Claims priority of provisional application 62/586,116, filed on Nov. 14, 2017.
Prior Publication US 2023/0301075 A1, Sep. 21, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/28 (2006.01); H01L 21/762 (2006.01); H01L 21/765 (2006.01); H01L 23/00 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H10B 20/00 (2023.01); H10B 41/35 (2023.01); H10B 41/43 (2023.01); H10B 41/49 (2023.01)
CPC H10B 20/60 (2023.02) [H01L 21/76229 (2013.01); H01L 21/765 (2013.01); H01L 23/562 (2013.01); H01L 29/0649 (2013.01); H01L 29/40114 (2019.08); H01L 29/404 (2013.01); H01L 29/66825 (2013.01); H10B 41/35 (2023.02); H10B 41/43 (2023.02); H10B 41/49 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a semiconductor substrate;
a first device and a second device overlying the semiconductor substrate;
a first trench isolation structure (TIS) and a second TIS recessed into a top of the semiconductor substrate and between the first device and the second device, wherein the first TIS is between the first device and the second TIS; and
a first dummy ring completely overlying the second TIS and surrounding the first TIS.