US 12,127,391 B2
Semiconductor memory device
Teruhisa Sonohara, Yokkaichi Mie (JP); Shunichi Seno, Yokkaichi Mie (JP); Hiroki Tokuhira, Kawasaki Kanagawa (JP); and Fumitaka Arai, Yokkaichi Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 29, 2023, as Appl. No. 18/458,054.
Application 18/458,054 is a division of application No. 17/472,902, filed on Sep. 13, 2021, granted, now 11,778,808.
Claims priority of application No. 2021-064476 (JP), filed on Apr. 5, 2021.
Prior Publication US 2023/0413516 A1, Dec. 21, 2023
Int. Cl. G11C 11/24 (2006.01); G11C 11/406 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/30 (2023.02) [G11C 11/40615 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); H01L 21/02565 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a bit line;
a source line;
a first transistor and a second transistor connected in series between the bit line and the source line;
a first wiring connected to a gate electrode of the second transistor;
a third transistor connected between the first wiring and the bit line;
a capacitor connected to the first wiring;
a first signal line connected to a gate electrode of the first transistor;
a second signal line connected to the capacitor; and
a third signal line connected to a gate electrode of the third transistor, wherein at a first timing:
a first voltage is applied to the bit line,
a second voltage is applied to the first signal line,
a third voltage is applied to the second signal line, and
a fourth voltage is applied to the third signal line, at a second timing:
a fifth voltage different from the first voltage is applied to the source line,
a sixth voltage larger than the second voltage is applied to the first signal line,
a seventh voltage larger than the third voltage is applied to the second signal line, and
the fourth voltage is applied to the third signal line, and at a third timing:
the second voltage is applied to the first signal line,
the third voltage is applied to the second signal line, and
an eighth voltage larger than the fourth voltage is applied to the third signal line, wherein
the fifth voltage is smaller than the first voltage.