CPC H04W 72/542 (2023.01) [H04W 24/04 (2013.01); H04W 24/08 (2013.01); H04W 24/10 (2013.01); H04W 4/40 (2018.02)] | 18 Claims |
11. A transmitter comprising:
a processor circuit and a memory circuit,
wherein the memory is arranged to store instructions for the processor circuit,
wherein the processor circuit is arranged to provide a plurality of resources,
wherein the plurality of resources is allocated for transmissions,
wherein the transmissions comprise at least one first transmission and at least one second transmission,
wherein the at least one first transmission has a first priority level,
wherein the at least one second transmission has a second priority level,
wherein the first priority level is higher than the second priority level, and
wherein the processor circuit is arranged to reserve a portion of non-occupied resources from the plurality of resources for the at least one first transmission, and allocate reserved resources for an initial transmission of the at least one first transmission when an occupancy of the plurality of resources reaches a predefined threshold.
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