US 12,126,924 B2
Solid-state imaging device and imaging device
Takuya Hanada, Kumamoto (JP); Koya Tsuchimoto, Kumamoto (JP); Makoto Nakamura, Kumamoto (JP); Yuki Noda, Kumamoto (JP); Yusuke Murakawa, Kumamoto (JP); and Shin Kitano, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/797,817
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Jan. 28, 2021, PCT No. PCT/JP2021/002964
§ 371(c)(1), (2) Date Aug. 5, 2022,
PCT Pub. No. WO2021/161791, PCT Pub. Date Aug. 19, 2021.
Claims priority of application No. 2020-022430 (JP), filed on Feb. 13, 2020.
Prior Publication US 2023/0059890 A1, Feb. 23, 2023
Int. Cl. H04N 25/709 (2023.01); H01L 27/146 (2006.01); H04N 25/707 (2023.01)
CPC H04N 25/709 (2023.01) [H01L 27/14612 (2013.01); H01L 27/14643 (2013.01); H04N 25/707 (2023.01)] 10 Claims
OG exemplary drawing
 
1. A solid-state imaging device, comprising:
a plurality of photoelectric conversion elements arranged side by side in a first region;
a plurality of current-voltage conversion circuits that convert currents output from the plurality of photoelectric conversion elements into voltages, respectively;
a plurality of address event detection circuits that detect changes in the voltages output from the plurality of current-voltage conversion circuits, respectively;
first ground wiring that is provided in a second region located outside the first region and that supplies first ground potential to the plurality of photoelectric conversion elements; and
second ground wiring that is provided in the second region and that supplies second ground potential having a voltage value different from a voltage value of the first ground potential to the plurality of current-voltage conversion circuits,
wherein each current-voltage conversion circuit in the plurality of current-voltage conversion circuits includes a loop-shaped source follower circuit,
the source follower circuit including:
a first transistor, wherein a source of the first transistor is directly connected to a photoelectric conversion element of the plurality of photoelectric conversion elements, and wherein the source of the first transistor is connected to a substantial center of the photoelectric conversion element in a cross section obtained by cutting a stacked substrate in a stacking direction of the stacked substrate on which the plurality of photoelectric conversion elements is formed; and
a second transistor, wherein a gate of the second transistor is directly connected to the photoelectric conversion element, and wherein a drain of the second transistor is connected to a gate of the first transistor.