CPC H04N 19/70 (2014.11) [H04N 19/12 (2014.11); H04N 19/172 (2014.11); H04N 19/176 (2014.11); H04N 19/1883 (2014.11); H04N 19/60 (2014.11)] | 11 Claims |
5. A decoder comprising:
a processor; and
memory coupled with the processor, wherein the memory comprises instructions that when executed by the processor cause the decoder to perform operations comprising:
receiving a bit stream having an encoded video block encoded with a multiple transform selection, MTS, index;
receiving a set descriptor from the bit stream once per frame, once per sequence of frames, once per coding tree unit, or once per coding unit;
parsing the set descriptor to determine a predetermined set of indices;
parsing the MTS index to determine a value of the MTS index;
determining whether the value is one of a predetermined set of indices;
responsive to the value being one of the predetermined set of indices:
parsing a low frequency non-separable transform, LFNST, index from the bit stream to determine a value of the LFNST index, the value indicating whether a LFNST transform set is to be used in decoding the encoded video block; and
responsive to the value not being one of the predetermined set of indices:
setting the value of the LFNST index to a default value indicating no LFNST transform is to be used in decoding the encoded video block; and
decoding the encoded video block based on the value of the MTS index and the value of the LFNST index.
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