US 12,126,348 B2
Adjustable phase locked loop
Florian Neveu, Freising (DE)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 11, 2023, as Appl. No. 18/448,319.
Application 18/448,319 is a continuation of application No. 17/730,205, filed on Apr. 27, 2022, granted, now 11,870,448.
Claims priority of provisional application 63/246,413, filed on Sep. 21, 2021.
Prior Publication US 2023/0387921 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03L 7/093 (2006.01); H03L 7/089 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/093 (2013.01) [H03L 7/0893 (2013.01); H03L 7/099 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A phase locked loop (PLL) comprising:
a compensation circuit including:
a resistive element having a resistance adjustable to a center frequency of a PLL bandwidth; and
a capacitor circuit coupled to the resistive element;
a transconductance circuit including:
a first current source having a first current source output, wherein the first current source is configured to provide a first current at the first current source output responsive to the center frequency; and
a first error amplifier having a reference input, first and second amplifier inputs and a first amplifier output, wherein the first amplifier input is coupled to the first current source output, the second amplifier input is coupled to the capacitor circuit, the first error amplifier has a transconductance representative of the center frequency, and the second amplifier input is coupled to an intermediate terminal that provides a signal responsive to the resistance and to a difference between a clock signal and a feedback signal;
a second error amplifier having third and fourth amplifier inputs and a second amplifier output; and
an oscillator having an oscillator output, wherein the oscillator is configured to provide a signal at the oscillator output for generating the feedback signal.