US 12,126,345 B2
Clock enabler circuit
Yoshinori Tanaka, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/759,174
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Oct. 27, 2020, PCT No. PCT/JP2020/040269
§ 371(c)(1), (2) Date Jul. 20, 2022,
PCT Pub. No. WO2021/152938, PCT Pub. Date Aug. 5, 2021.
Claims priority of application No. 2020-012092 (JP), filed on Jan. 29, 2020.
Prior Publication US 2023/0043523 A1, Feb. 9, 2023
Int. Cl. H03K 5/15 (2006.01); H03K 5/131 (2014.01); H03K 19/096 (2006.01)
CPC H03K 5/15006 (2013.01) [H03K 5/131 (2013.01); H03K 19/096 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A clock enabler circuit, comprising:
a state holding unit configured to perform, based on an internal clock signal, a holding operation of a state, wherein the state indicates whether to output an output clock signal;
a clock signal output unit configured to control the output of the output clock signal based on the state held in the state holding unit; and
a control unit configured to:
receive a clock signal and a clock enable signal from an outside of the control unit; and
supply, to the state holding unit, the internal clock signal and a value of the state that are for the holding operation, wherein
the supply is based on the clock signal and the clock enable signal, and
the state holding unit includes a delay unit configured to delay a timing at which the value of the state is supplied to the state holding unit.