US 12,126,309 B2
Methods and apparatus for voltage buffering
Siraj Akhtar, Richardson, TX (US); and Swaminathan Sankaran, Allen, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 30, 2019, as Appl. No. 16/557,571.
Claims priority of provisional application 62/725,832, filed on Aug. 31, 2018.
Prior Publication US 2020/0076374 A1, Mar. 5, 2020
Int. Cl. H03F 1/26 (2006.01); H03F 3/183 (2006.01); H03F 3/45 (2006.01); H03H 11/28 (2006.01); H03F 1/30 (2006.01); H03F 3/50 (2006.01)
CPC H03F 1/26 (2013.01) [H03F 3/183 (2013.01); H03H 11/28 (2013.01); H03F 1/306 (2013.01); H03F 3/505 (2013.01); H03F 2200/03 (2013.01); H03F 2200/318 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a voltage follower circuit having a voltage follower input, a power terminal, and a voltage follower output, the voltage follower circuit including a first transistor coupled between the power terminal and the voltage follower output, the first transistor including a bipolar junction transistor BJT) and having a first control terminal coupled to the voltage follower input;
an inductor having first and second inductor terminals, the first inductor terminal coupled to a ground terminal; and
a current source coupled between the voltage follower output and the second inductor terminal, the current source including a second transistor, the second transistor including a field effect transistor (FET) and having a second control terminal coupled to a bias input.