CPC H01L 31/1812 (2013.01) [H01L 31/02016 (2013.01); H01L 31/1864 (2013.01); H01L 31/1868 (2013.01)] | 20 Claims |
1. A method of manufacturing a semiconductor structure, the method comprising:
etching a trench in a substrate;
forming a light-absorption layer in the trench;
forming a first doped region of a first conductivity type and a second doped region of a second conductivity type in the light-absorption layer adjacent to the first doped region;
depositing a first patterned mask layer over the light-absorption layer, wherein the first patterned mask layer includes an opening exposing the second doped region and covers the first doped region;
forming a first silicide layer in the opening on the second doped region;
depositing a barrier layer over the first doped region; and
annealing the barrier layer to form a second silicide layer on the first doped region.
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