US 12,125,921 B2
Semiconducting metal oxide transistors having a patterned gate and methods for forming the same
Yong-Jie Wu, Tainan (TW); Hui-Hsien Wei, Taoyuan (TW); Yen-Chung Ho, Hsinchu (TW); Mauricio Manfrini, Hsinchu (TW); Chia-Jung Yu, Hsinchu (TW); Chung-Te Lin, Taiwan (TW); and Pin-Cheng Hsu, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jul. 19, 2023, as Appl. No. 18/354,681.
Application 18/354,681 is a continuation of application No. 17/216,747, filed on Mar. 30, 2021, granted, now 11,757,047.
Claims priority of provisional application 63/031,720, filed on May 29, 2020.
Prior Publication US 2023/0361221 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 29/401 (2013.01); H01L 29/41733 (2013.01); H01L 29/41775 (2013.01); H01L 29/42364 (2013.01); H01L 29/42384 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/7869 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a first dielectric layer;
a gate electrode embedded in the first dielectric layer;
a gate dielectric layer;
a channel layer disposed on the gate dielectric layer and comprising a semiconducting metal oxide material; and
a source electrode and a drain electrode contacting a top surface of the channel layer,
wherein:
the first dielectric layer comprises a top horizontal surface that contacts the gate dielectric layer and a recessed horizontal surface that does not underlie the gate dielectric layer; and
a set of sidewall segments of the first dielectric layer adjoins the top horizontal surface of the first dielectric layer to the recessed horizontal surface of the first dielectric layer.