US 12,125,920 B2
Dual-layer channel transistor and methods of forming same
Hung Wei Li, Hsinchu (TW); Yu-Ming Lin, Hsinchu (TW); Mauricio Manfrini, Zhubei (TW); Kuo-Chang Chiang, Hsinchu (TW); and Sai-Hooi Yeong, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Mar. 28, 2023, as Appl. No. 18/191,567.
Application 18/191,567 is a continuation of application No. 17/228,392, filed on Apr. 12, 2021, granted, now 11,646,379.
Claims priority of provisional application 63/042,581, filed on Jun. 23, 2020.
Prior Publication US 2023/0238462 A1, Jul. 27, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 29/1054 (2013.01); H01L 29/66765 (2013.01); H01L 29/66969 (2013.01); H01L 29/78669 (2013.01); H01L 29/78678 (2013.01); H01L 29/7869 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transistor, comprising:
a gate electrode;
a gate dielectric layer disposed on the gate electrode;
a first channel layer disposed on the gate dielectric layer and having a first electrical resistance;
a second channel layer covering top and side surfaces of the first channel layer; and
a source electrode and a drain electrode that are electrically coupled to the second channel layer,
wherein the first channel layer has a higher electrical resistance than the second channel layer, such that when a voltage is applied to the gate electrode more current flows through the second channel layer than through the first channel layer.