US 12,125,908 B2
Semiconductor device and method
Chia-Ling Chan, New Taipei (TW); Meng-Yueh Liu, Taoyuan (TW); and Wei-Ken Lin, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 23, 2022, as Appl. No. 17/751,198.
Application 17/751,198 is a continuation of application No. 16/908,305, filed on Jun. 22, 2020, granted, now 11,342,454.
Application 16/908,305 is a continuation of application No. 15/816,259, filed on Nov. 17, 2017, granted, now 10,700,197, issued on Jun. 30, 2020.
Claims priority of provisional application 62/565,752, filed on Sep. 29, 2017.
Prior Publication US 2022/0285552 A1, Sep. 8, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 21/225 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7833 (2013.01) [H01L 21/2254 (2013.01); H01L 21/31111 (2013.01); H01L 21/31133 (2013.01); H01L 21/31144 (2013.01); H01L 21/31155 (2013.01); H01L 21/823821 (2013.01); H01L 29/0649 (2013.01); H01L 29/66492 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first gate stack on a first semiconductor fin and a second gate stack on a second semiconductor fin, the first semiconductor fin and the second semiconductor fin protruding above an isolation region;
depositing a spacer layer on the first gate stack, the second gate stack, the first semiconductor fin, the second semiconductor fin, and the isolation region;
forming a mask on the spacer layer, the mask covering the second semiconductor fin, the first semiconductor fin uncovered by the mask;
implanting a first dopant having a first doping type in the spacer layer over the first semiconductor fin while the mask shields the spacer layer over the second semiconductor fin;
performing an anneal process to drive the first dopant from the spacer layer into the first semiconductor fin and the isolation region, wherein the spacer layer covers the first semiconductor fin and the isolation region during the anneal process; and
after performing the anneal process, patterning the spacer layer to form a first gate spacer and a second gate spacer, the first gate spacer extending along a sidewall of the first gate stack, the second gate spacer extending along a sidewall of the second gate stack.