US 12,125,889 B2
Source/drain contact with low-k contact etch stop layer and method of fabricating thereof
Ting-Yeh Chen, Hsinchu (TW); Wei-Yang Lee, Taipei (TW); Chia-Pin Lin, Hsinchu County (TW); and Da-Wen Lin, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Sep. 2, 2021, as Appl. No. 17/465,665.
Claims priority of provisional application 63/157,165, filed on Mar. 5, 2021.
Prior Publication US 2022/0285513 A1, Sep. 8, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823468 (2013.01); H01L 29/0665 (2013.01); H01L 29/6656 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a semiconductor device including a gate stack disposed over a channel region of the semiconductor device;
forming a gate spacer on a sidewall of the gate stack;
forming a source/drain feature in a source/drain region of the semiconductor device, wherein the source/drain feature is adjacent the gate spacer;
after forming the source/drain feature, performing an etch process to remove a first portion of the gate spacer, wherein a second portion of the gate spacer remains between the sidewall of the gate stack and the source/drain feature;
forming a contact etch stop layer on the gate spacer, wherein the contact etch stop layer is disposed on a top surface of the second portion of the gate spacer; and
forming a source/drain contact on the source/drain feature and adjacent the contact etch stop layer.