US 12,125,867 B2
Imaging device and electronic device
Hajime Yamagishi, Kanagawa (JP); Shota Hida, Nagasaki (JP); and Yuusaku Kobayashi, Nagasaki (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Sep. 20, 2023, as Appl. No. 18/370,593.
Application 18/370,593 is a continuation of application No. 17/459,873, filed on Aug. 27, 2021, granted, now 11,817,471.
Application 17/459,873 is a continuation of application No. 16/614,955, granted, now 11,133,343, issued on Sep. 28, 2021, previously published as PCT/JP2018/017477, filed on May 2, 2018.
Claims priority of application No. 2017-104991 (JP), filed on May 26, 2017.
Prior Publication US 2024/0088188 A1, Mar. 14, 2024
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/14634 (2013.01) [H01L 27/14636 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An imaging device, comprising:
a first substrate including:
a first semiconductor layer including a photoelectric conversion region that converts incident light into an electric charge; and
a first multilayer wiring layer electrically connected to the photoelectric conversion region; and
a second substrate including:
a second semiconductor layer including a plurality of transistors; and a second multilayer wiring layer electrically connected to the plurality of transistors; and
a third layer including a wiring layer,
wherein the first multilayer wiring layer or the second multilayer wiring layer includes a first vertical signal line (VSL1) to output a first pixel signal based on the electric charge, and
wherein the second multilayer wiring layer includes a first wiring that is connected to a second wiring in the third layer through a conductive via, and wherein the first wiring, the second wiring, and the conductive via are located in a peripheral portion of imaging device.