US 12,125,850 B2
Buried metal track and methods forming same
Pochun Wang, Hsinchu (TW); Ting-Wei Chiang, New Taipei (TW); Chih-Ming Lai, Hsinchu (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Jung-Chan Yang, Longtan Township (TW); Ru-Gun Liu, Zhubei (TW); Shih-Ming Chang, Hsinchu (TW); Ya-Chi Chou, Hsinchu (TW); Yi-Hsiung Lin, Zhubei (TW); Yu-Xuan Huang, Hsinchu (TW); Guo-Huei Wu, Tainan (TW); and Yu-Jung Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 19, 2021, as Appl. No. 17/234,256.
Application 17/234,256 is a continuation of application No. 16/515,709, filed on Jul. 18, 2019, granted, now 11,004,855.
Application 16/515,709 is a continuation of application No. 15/691,974, filed on Aug. 31, 2017, granted, now 10,446,555, issued on Oct. 15, 2019.
Prior Publication US 2021/0242212 A1, Aug. 5, 2021
Int. Cl. H01L 27/088 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01); H10B 12/00 (2023.01); H01L 27/092 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/76897 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 23/522 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 29/785 (2013.01); H10B 12/31 (2023.02); H10B 12/36 (2023.02); H01L 27/0924 (2013.01); H10B 12/34 (2023.02); H10B 12/37 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a bulk semiconductor substrate;
an isolation region over the bulk semiconductor substrate;
a first semiconductor fin over the isolation region;
a buried conductive track comprising at least a portion in the isolation region;
a transistor comprising:
a gate electrode over the first semiconductor fin;
a source/drain region on a side of the gate electrode, wherein the buried conductive track extends underlying the gate electrode, and at least a portion of the buried conductive track is lower than the source/drain region, and wherein the buried conductive track is connected to at least one of the gate electrode and the source/drain region;
a source/drain contact plug extending down to physically contact the buried conductive track; and
a source/drain silicide region between and contacting the source/drain contact plug and the source/drain region; and
a dielectric layer comprising:
a bottom portion directly underlying the buried conductive track; and
sidewall portions on opposing sides of, and contacting sidewalls of, the buried conductive track.