US 12,125,824 B2
Semiconductor stack structure and manufacturing method thereof
Chuei-Tang Wang, Taichung (TW); Chien-Yuan Huang, Hsinchu (TW); and Shih-Chang Ku, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 30, 2022, as Appl. No. 17/855,726.
Prior Publication US 2024/0006379 A1, Jan. 4, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01)
CPC H01L 25/0655 (2013.01) [H01L 24/89 (2013.01); H01L 2224/80894 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor stack structure, comprising:
a first semiconductor element;
a second semiconductor element side-by-side bonded to the first semiconductor element through a direct bonding manner, wherein a bond thickness of a dielectric interface of the first semiconductor element and the second semiconductor element is equal to or less than 20 μm; and
a third semiconductor element, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element.