CPC H01L 25/0655 (2013.01) [H01L 23/3185 (2013.01); H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 25/50 (2013.01); H01L 2224/16157 (2013.01)] | 20 Claims |
1. A method for forming a semiconductor device package, comprising:
bonding a first package component and a second package component to a substrate, wherein the first and second package components are different types of electronic components that provide different functions, wherein the first package component is a processor die and the second package component is a memory die;
attaching at least one dummy die to the substrate, wherein the dummy die is located between the first and second package components and is electrically isolated from the substrate, wherein the first package component and the second package component are disposed on two opposite sides of the dummy die;
disposing an underfill element between the substrate, the first package component, the second package component, and the dummy die, wherein the dummy die has a greater modulus of elasticity than the underfill element, wherein the dummy die is homogeneous bulk copper or homogeneous bulk stainless steel, and
wherein the underfill element extends up along all sidewalls of the dummy die and laterally surrounds all the sidewalls of the dummy die in a top view, wherein a top surface of the dummy die is higher than the top surface of the underfill element in a vertical direction such that the top surface and portions of all the sidewalls of the dummy die are exposed from the underfill element, wherein the underfill element has a maximum height lower than the top surface of the dummy die; and
forming an encapsulant on the substrate to cover the first package component, the second package component, the dummy die, and the underfill element, wherein the top surface and the portions of all the sidewalls of the dummy die exposed from the underfill element are in direct contact with the encapsulant.
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