US 12,125,794 B2
Semiconductor device and manufacturing method of semiconductor device
Chih-Hang Tung, Hsinchu (TW); Chen-Hua Yu, Hsinchu (TW); Tung-Liang Shao, Hsinchu (TW); Su-Chun Yang, Hsinchu County (TW); and Wen-Lin Shih, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 12, 2023, as Appl. No. 18/167,879.
Application 18/167,879 is a continuation of application No. 17/884,579, filed on Aug. 10, 2022.
Application 17/884,579 is a continuation of application No. 16/885,282, filed on May 28, 2020, granted, now 11,456,256, issued on Sep. 27, 2022.
Prior Publication US 2023/0207473 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 21/50 (2006.01); H01L 21/768 (2006.01); H01L 23/373 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5384 (2013.01) [H01L 21/50 (2013.01); H01L 21/76802 (2013.01); H01L 21/76841 (2013.01); H01L 21/76877 (2013.01); H01L 23/3736 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate;
an electrical insulating and thermal conductive layer disposed over the semiconductor substrate;
an etch stop layer comprising silicon nitride and disposed between the semiconductor substrate and the electrical insulating and thermal conductive layer;
a dielectric structure disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure; and
a circuit layer damascened in the dielectric structure, wherein the circuit layer comprises a bottom surface closest to the semiconductor substrate, and a lower surface of the etch stop layer is substantially coplanar with the bottom surface of the circuit layer.