US 12,125,763 B2
Trim wall protection method for multi-wafer stacking
Sheng-Chan Li, Tainan (TW); Cheng-Hsien Chou, Tainan (TW); Sheng-Chau Chen, Tainan (TW); Cheng-Yuan Tsai, Chu-Pei (TW); and Kuo-Ming Wu, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 8, 2023, as Appl. No. 18/331,249.
Application 18/331,249 is a continuation of application No. 17/501,418, filed on Oct. 14, 2021, granted, now 11,715,674.
Application 17/501,418 is a continuation of application No. 16/785,866, filed on Feb. 10, 2020, granted, now 11,152,276, issued on Oct. 19, 2021.
Claims priority of provisional application 62/928,497, filed on Oct. 31, 2019.
Prior Publication US 2023/0317541 A1, Oct. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/3185 (2013.01) [H01L 21/56 (2013.01); H01L 21/76829 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 25/0657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip structure, comprising:
a substrate;
an interconnect structure on the substrate, wherein the interconnect structure comprises a plurality of interconnects disposed within a dielectric structure;
a dielectric protection layer along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate; and
wherein a bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate, and wherein the dielectric protection layer has a thickness that is greater than or equal to approximately 200 angstroms.