US 12,125,748 B2
Contact plug
Chih-Hsuan Lin, Hsinchu (TW); Xi-Zong Chen, Tainan (TW); and Chih-Teng Liao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 20, 2022, as Appl. No. 17/868,927.
Application 17/868,927 is a continuation of application No. 17/142,750, filed on Jan. 6, 2021, granted, now 11,798,846.
Claims priority of provisional application 63/071,194, filed on Aug. 27, 2020.
Claims priority of provisional application 63/065,630, filed on Aug. 14, 2020.
Prior Publication US 2022/0367269 A1, Nov. 17, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 21/285 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/28518 (2013.01); H01L 21/76829 (2013.01); H01L 21/76846 (2013.01); H01L 21/7685 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a source/drain feature;
a first etch stop layer over the source/drain feature;
a first dielectric layer over the first etch stop layer;
a second etch stop layer over the first dielectric layer and the first etch stop layer;
a second dielectric layer over the second etch stop layer;
a source/drain contact comprising:
a lower portion extending through the first etch stop layer and the first dielectric layer, and
an upper portion disposed on the lower portion, the upper portion extending through the second etch stop layer and the second dielectric layer;
a first metal liner disposed between the lower portion and the first dielectric layer;
a dielectric barrier layer extending between the first metal liner and the first dielectric layer as well as between the first metal liner and the first etch stop layer; and
a second metal liner disposed between the upper portion and the second dielectric layer,
wherein a composition of the first metal liner is different from a composition of the second metal liner.