US 12,125,746 B2
Passivation layer for integrated circuit structure and forming the same
Chun-Chiang Chen, Hsinchu (TW); Chun-Ting Wu, Kaohsiung (TW); Ching-Hou Su, Hsinchu (TW); and Chih-Pin Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on May 15, 2023, as Appl. No. 18/317,759.
Application 18/317,759 is a continuation of application No. 17/378,566, filed on Jul. 16, 2021, granted, now 11,688,633.
Application 17/378,566 is a continuation of application No. 16/744,014, filed on Jan. 15, 2020, granted, now 11,069,562, issued on Jul. 20, 2021.
Prior Publication US 2023/0307292 A1, Sep. 28, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01)
CPC H01L 21/76832 (2013.01) [H01L 21/02274 (2013.01); H01L 21/76834 (2013.01); H01L 23/5226 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13024 (2013.01)] 20 Claims
OG exemplary drawing
 
11. An integrated circuit (IC) structure, comprising:
a metal line laterally extending over a substrate;
a liner over the metal line;
a passivation layer over the liner, the passivation layer being less porous than the liner;
an under bump metallurgy (UBM) layer extending through the passivation layer and the liner to the metal line; and
a pillar over the UBM layer.