US 12,125,741 B2
Semiconductor package and method of fabricating semiconductor package
Zi-Jheng Liu, Taoyuan (TW); Chen-Cheng Kuo, Shin-Chu County (TW); and Hung-Jui Kuo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 1, 2023, as Appl. No. 18/362,968.
Application 18/362,968 is a division of application No. 17/185,978, filed on Feb. 26, 2021, granted, now 11,862,512.
Application 17/185,978 is a continuation of application No. 16/396,793, filed on Apr. 29, 2019, granted, now 10,937,688, issued on Mar. 2, 2021.
Application 16/396,793 is a continuation of application No. 15/688,817, filed on Aug. 28, 2017, granted, now 10,276,428, issued on Apr. 30, 2019.
Prior Publication US 2023/0377951 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/053 (2006.01); H01L 21/02 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/76807 (2013.01) [H01L 21/02645 (2013.01); H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/5329 (2013.01); H01L 23/5384 (2013.01); H01L 24/32 (2013.01); H01L 2221/1015 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/32225 (2013.01); H01L 2924/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, comprising:
providing a substrate having at least one contact therein and a dielectric material layer thereon;
performing a double exposure process to the dielectric material layer including sequentially performing a first exposure process to form first exposure portions in the dielectric material layer and performing a second exposure process to form second exposure portions in the dielectric material layer;
performing a development process to dissolve the first and second exposure portions and over-develop the dielectric material layer to form a dual damascene opening with a via opening and a trench opening communicated with the via opening, wherein a slant sidewall of the via opening is connected with a slant sidewall of the trench opening, and the slant sidewall of the via opening has the same slope as the slant sidewall of the trench opening;
forming a seed metallic layer into the dual damascene opening and over the dielectric material layer; and
forming a metallic pattern filled in the dual damascene opening.