US 12,125,712 B2
Landing metal etch process for improved overlay control
Chih-Min Hsiao, Hsinchu (TW); Chih-Ming Lai, Hsinchu (TW); Chien-Wen Lai, Hsinchu (TW); Ya Hui Chang, Hsinchu (TW); and Ru-Gun Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/227,858.
Application 17/735,073 is a division of application No. 16/688,681, filed on Nov. 19, 2019, granted, now 11,322,362, issued on May 3, 2022.
Application 18/227,858 is a continuation of application No. 17/735,073, filed on May 2, 2022, granted, now 11,798,812.
Claims priority of provisional application 62/774,125, filed on Nov. 30, 2018.
Prior Publication US 2023/0377900 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 21/31144 (2013.01) [H01L 21/76808 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
depositing a hard mask layer on an upper surface of an insulating layer;
etching the hard mask layer to form an opening in the hard mask layer;
forming a via recess in the hard mask layer through the opening;
forming a first photoresist layer on the hard mask layer and in the via recess;
etching the first photoresist layer to form a photoresist plug in the via recess;
etching two opposite sides of the opening to remove portions of the hard mask layer and thereby expose a portion of the upper surface of the insulating layer;
removing the photoresist plug;
depositing metal in the via recess, in the opening, and on the exposed upper surface of the insulating layer; and
patterning the metal over the via recess to form a metal line that is in contact with at least the metal in the opening, wherein an axis of the metal line is offset from the center of the via recess.